The present invention relates to techniques for biasing amplification transistors, and in particular, techniques designed to adjust the bias current to compensate for induced bias drift caused by temperature and hot-carrier injection.
In amplification circuits, it is highly desirable for amplification transistors to have a stable bias current in order to maintain a particular level of performance. Deviations from a particular bias current level degrades the overall performance of the amplification transistor. In particular, deviation from the original quiescent current point degrades the gain performance of the amplification circuit. Bias current drift also increases the signal distortion and degrades the linear performance of the transistor. In applications such as cellular base stations that utilize the amplification circuit, any significant performance degradation in the amplification transistors inhibits the ability of the base station to function.
There are a number of phenomena that will cause the bias current in the amplification transistor to drift. Variations in temperature will cause short term drift in the bias current. In addition, variations in the power supply will cause short term drift. Long term drift in the bias current is caused by Hot Carrier Injection (HCI).
HCI induced bias drift is a phenomenon that degrades the performance of Metal-Oxide Semiconductor (MOS) transistors and Laterally Diffused MOS transistors (LDMOS) in particular. The term hot carriers refers to carriers that arc highly energetic. When an electric field is applied across the source and drain of the MOS device, carriers become accelerated and undergo drift. Typically, most of these electrons will experience one or more scattering events when undergoing transport in the channel between the source and drain. However, as MOS devices are reduced in scale and the distance between the source and drain is decreased, more and more carriers travel from the source to the drain while experiencing fewer and fewer scattering events. These carriers that fail to encounter as many scattering events then become highly energetic and cause Hot Carrier Injection (HCI) in the source and drain. The HCI effect causes the bias current to drift away from a desired quiescent point. This drift of the quiescent current is highly undesirable. Under the HCI effect, the level of bias current can drift to either a higher level or a lower level of current. In addition, the HCI effect causes the bias current to drift away from its initial setting up to 20 percent at a constant power supply condition.
For a reliable operation of the base stations, all devices used in the station should sustain a satisfactory performance for at least twenty years. To provide this twenty year period of satisfactory performance, solutions have evolved to keep the quiescent point of the amplification transistor stable independent of temperature, power supply variations, and HCI. One of these techniques is to use an active bias network, which is a closed loop control system. The active bias network regulates the flow of bias current in particular transistor, referred to as the xe2x80x9ctargetedxe2x80x9d transistor, by simulating the behavior of the targeted transistor with an external circuit. The external circuit simulates the behavior of the targeted transistor with a reference transistor that is a scaled replica of the targeted transistor. Through making the reference transistor a scaled replica of the targeted transistor, it is possible to replicate the variations in the bias current in the targeted transistor caused by HCI, temperature fluctuations, and power supply variations in the reference transistor.
The current variations in the reference transistor, which are proportional to the current variations in the targeted transistor, are detected by a current sensing circuit. When the active bias network detects a bias change in the reference transistor, which is indicative of the bias change in the targeted transistor, the circuit provides a corrective feedback to both the targeted and reference transistors to restore them both to providing the desired level of bias current.
There are two basic techniques employed to sense bias current changes in the reference transistor. Bias variations are detected through sensing either voltage or current changes in the reference transistor. With either technique, a primary concern is creating a bias current sensor that does not prevent the reference transistor from accurately simulating the targeted transistor. For the reference transistor to accurately simulate the operation of the targeted transistor, it is necessary for the reference transistor to have the same design ratio and the same voltage loading as the targeted transistor. The HCI effect in MOS transistors is related to several factors including gate oxide degradation, process induced damage, and a high electric field concentration in the channel between the source and drain in the MOS device. If the reference transistor has a different voltage loading than the targeted transistor, the reference transistor will have a different amount of electric field concentration in the channel and a different level of HCI and react differently to temperature and power supply fluctuations. Consequently, the reference transistor will not accurately replicate the function of the targeted transistor, thereby preventing the active bias network from properly stabilizing the targeted transistor at a specified current level.
Designing a reference transistor with a design ratio identical to the targeted transistor is a straight forward matter. However, designing a bias current sensor that minimizes the xe2x80x9cheadroom effectxe2x80x9d is a more complex problem. The headroom effect refers to the voltage loading across the sensing device that is connected to the reference transistor. Both the reference transistor and the targeted transistor are connected to the same power supply. If there is zero voltage drop across the current sensing device, then the voltage drop across the reference transistor is identical to the voltage drop across the targeted transistor. As a result, the reference transistor precisely simulates the operation of the targeted transistor. However, when the current sensing device begins to consume voltage and reduce the loading across the reference transistor, the performance of the reference transistor begins to deviate from the targeted transistor. When the current sensor takes a portion of the loading that would preferably fall across the reference transistor, the current sensor begins to occupy xe2x80x9cheadroom.xe2x80x9d The performance of the active bias network is maximized when the headroom effect is minimized.
The active bias method disclosed in the U.S. Pat. No. 6,046,642 issued to Brayton et al. utilizes a resistor to sense the level of current flowing through the monitored reference transistor. Voltage changes across this sensing resistor indicate bias current changes occurring in the reference and targeted transistors. The active bias system in the U.S. Pat. No. 6,042,642 patent uses this sensed information to provide feedback to the monitored transistor and restore the bias current to its desired level.
The use of a sense resistor to monitor the level of current flowing from the reference transistor has numerous implications for the effectiveness for the active bias network. The use of a sense resistor directly impacts the loading on the reference transistor. It is desirable to use a large sense resistor to detect the current flowing in the reference transistor because of the relatively small amount of circuitry needed to monitor the level of current. However, the use of a large sense resistor to detect the bias current from the reference transistor produces a large voltage drop across the sense resistor. The size of this voltage drop is as large as two Volts. Consequently, the use of a large sense resistor makes the loading across the reference transistor different from the targeted transistor. When a transistor may only have a turn on voltage of two volts, the presence of the sensing resistor with a loading of two volts greatly disturbs the ability of the reference transistor to replicate the functions of the targeted transistor. As a result, the reference transistor does not precisely emulate the current variations in the targeted transistor due to temperature, power fluctuations, and HCI.
One solution to this loading problem is to use a small resistor as a current sensor. A small resistor has a small voltage drop that enables the reference transistor to closely emulate the targeted transistor. However, a small sense resistor has the disadvantage of requiring a large circuit to detect the small voltage drop across the small sense resistor. This large circuit consumes a large amount of chip space and requires a significant amount of design time to properly implement.
It is also possible to implement an active bias network utilizing current mirrors to sense and control bias current in the reference and targeted transistors. A current mirror in its most basic form consists of a transistor pair that produces a controlled current flowing in a transistor that is a multiple of a reference current flowing in the other transistor. The two transistors in the current mirror will carry the same level of current if they share the same dimensions and the same gate/drain bias voltages.
The current mirrors used in active bias networks known to the art have the transistor pair of the current mirror operating in the saturation region. In order to place the transistor pair into the saturation region, it is necessary to place a bias of VDS across the drain/source terminals of the transistors. Typically VDS is on the order of 2 volts.
As noted earlier, for the reference transistor to duplicate any HCI induced bias drift in the targeted transistor, it is necessary to keep similar drain/source bias voltages across the two transistors. However, with the transistor pair requiring a bias voltage of approximately.2 volts, at least 2 volts or more of voltage headroom is needed to bias the reference transistor. For a fixed voltage supply, the headroom occupied by the current mirror causes a 2 volt or more source/drain bias difference between the reference transistor and the targeted transistor. Since the current mirror alters the bias across the reference transistor, the electric field in the channel of the reference transistor is different from the targeted transistor. As a result, the reference transistor has a different level of HCI than the targeted transistor preventing the reference transistor from accurately simulating the targeted transistor.
The cause for this inability of the reference transistor to accurately simulate the targeted transistor is the headroom occupied by the current mirror. Consequently, there is a need to develop a new active bias network that can monitor and correct bias current changes in a targeted transistor more accurately while minimizing the headroom effect and minimizing the amount of circuitry used.
The present invention is for an active current bias network that compensates for Hot-Carrier Injection (HCI) induced bias drift, a common phenomenon existing in Metal-Oxide Semiconductor (MOS) transistors and especially in Laterally Diffused MOS (LDMOS) transistors. The active bias network of the present invention first senses the bias current flowing in the targeted transistor and then compares the bias current in the targeted transistor with a stable reference current. The difference between the bias current in the targeted transistor and the reference current is then utilized to adjust the bias of the targeted transistor via a current mirror feedback circuit.
The bias current of the targeted transistor then is stable independent of any HCI induced bias changes and changes due to other adverse causes. The sensing MOS transistor used for monitoring bias current is operated in the triode region and has minimum effect on the performance of the targeted transistor.
The present invention is also applicable to bias devices manufactured by other technologies like Bipolar Junction Transistors (BJT), Hetero-Junction Bipolar Transistors (HBT), Metal Semiconductor Field Effect Transistors (MESFET) and High Electron Mobility Transistors (HEMT). In addition, the present invention can be implemented in monolithic circuitry on the microchip or in discrete circuitry external of the microchip.